The present invention relates to semiconductor memory devices, and more particularly, to the testing of semiconductor memory devices having memory modules.
High speed semiconductor memory devices are partially designed to receive or transmit input and output signals such as data or addresses through a bus-type transmission line. In the bus-type structure, various semiconductor memory devices are connected in common to one bus, and only one semiconductor memory device can load data onto the bus at the time. If two or more semiconductor memory devices simultaneously attempt to load data onto the bus, the data collides with each other, which causes a malfunction.
A Rambus dynamic random access memory (DRAM), which is a type of high speed semiconductor memory device, employs the above-described bus-type structure, as well as a proposed special module for supporting the bus-type structure. FIG. 1 is a block diagram of a Rambus DRAM memory module having the bus-type structure.
Referring to FIG. 1, a memory module 200 includes a plurality of semiconductor memory devices M.sub.1 through M.sub.n, each having a plurality of input and output pins DQ.sub.1 to DQ.sub.w, i.e., Rambus DRAMs. Furthermore, identical input and output pins of the semiconductor memory devices M.sub.1 to M.sub.n are connected in common to a corresponding data bus. In other words, first input and output pins DQ.sub.1 of each of the semiconductor memory devices M.sub.1 to M.sub.n are connected in common to a data bus DB.sub.1 ; second input and output pins DQ.sub.2 are connected in common to a data bus DB.sub.2 ; and so on until W.sup.th input and output pins DQ.sub.w of the semiconductor memory devices M.sub.1 to M.sub.n are connected in common to a w.sup.th data bus DB.sub.w. Input and output pins of a controller 100, which is a master controller, are connected to corresponding data buses.
In the memory module having the bus-type structure of FIG. 1, identical data can be simultaneously written to various semiconductor memory devices during a write operation. However, when data is simultaneously read from two or more semiconductor memory devices during a read operation, the data collides with each other on the data bus. As a result, data may only be read from one semiconductor memory devices at a time.
FIG. 2 is a block diagram of a conventional output data merge circuit which is in each of the semiconductor memory devices of FIG. 1. Referring to FIG. 2, during a normal mode, a plurality of output data DO.sub.1 to DO.sub.w read from a memory cell array 21 are simultaneously output through a plurality of output pins DQ.sub.1 through DQ.sub.w. During a test mode, however, a comparator 22 merges the plurality of output data DO.sub.1 through DO.sub.w read from the memory cell array 21 and outputs the result to a single predetermined output pin, e.g., DQ.sub.1.
Thus, when the semiconductor memory devices, including the output data merge circuit of FIG. 2, are employed as the memory modules of FIG. 1, all of the semiconductor memory devices output their data to a data bus, e.g., a data bus DB.sub.1 through a predetermined output pin DQ.sub.1 during read operations of a test mode. Thus, when the data is read from two or more semiconductor memory devices, the data collide with each other on the data bus DB.sub.1.
As a result, when the semiconductor memory devices, including the conventional output data merge circuit, are employed in the memory module of FIG. 1, the data must be read from only one semiconductor memory device at a time during testing of the memory module. In other words, only one semiconductor memory device can be tested at a time, so that memory module time is lengthened.